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NCP1605 Enhanced, High Voltage and Efficient Standby Mode, Power Factor Controller
The NCP1605 is a controller that exhibits near-unity power factor while operating in fixed frequency, Discontinuous Conduction Mode (DCM) or in Critical Conduction Mode (CRM). Housed in a SOIC-16 package, the circuit incorporates all the features necessary for building robust and compact PFC stages, with a minimum of external components. In addition, it integrates the skip cycle capability to lower the standby losses to a minimum.
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MARKING DIAGRAM
1 16 SOIC-16 D SUFFIX CASE 751B 1 A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package NCP1605 AWLYWWG
* * * * * * * * * * * * * * * * * * * * *
Near-Unity Power Factor Fixed Frequency, Discontinuous Conduction Mode Operation Critical Conduction Mode Achievable in Most Stressful Conditions Lossless High Voltage Current Source for Startup Soft Skipt Cycle for Low Power Standby Mode Switching Frequency up to 250 kHz Synchronization Capability Fast Line / Load Transient Compensation Valley Turn On High Drive Capability: -500 mA / +800 mA Signal to Indicate that the PFC is Ready for Operation ("pfcOK" Pin) VCC range: from 10 V to 20 V Follower Boost Operation This is a Pb-Free Device
PIN CONNECTIONS
STBY 1 BO 2 Vcontrol 3 FB 4 CSin 5 CSout/ZCD 6 Ct 7 OSC/SYNC 8 (Top View) 16 HV 15 NC 14 OVP/UVP 13 STDWN 12 pfcOK/REF5V 11 VCC 10 DRV 9 GND
Safety Features
Output Under and Overvoltage Protection Brown-Out Detection Soft-Start for Smooth Startup Operation Overcurrent Limitation Zero Current Detection Protecting the PFC stage from Inrush Currents Thermal Shutdown Latched Off Capability
ORDERING INFORMATION
Device NCP1605DR2G Package SOIC-16 (Pb-Free) Shipping 2500/T ape & Reel
Typical Applications
* PC Power Supplies * All Off Line Appliances Requiring Power Factor Correction
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2007
1
February, 2007 - Rev. 1
Publication Order Number: NCP1605/D
NCP1605
Rbo1 Rbo2
Rout1 Rout2 STBY control 1 16 2 15
Vout Rovp1
VCC + CVCC L1
Vin Icoil
Cbo CVctrl Rzcd Ac line Cin EMI Filter Rocp Cosc Ct FB
3 14 4 13 5 12 6 11 7 10 8 9
OVP
Rovp2 D1
Vout
VCC
CVref pfcOK
M1 Cbulk +
LOAD
Rdrv
Icoil
Rcs
Figure 1.
MAXIMUM RATINGS
Pin 10 10 1, 2, 4, 6, 7, 8, 13 and 14 3 16 Power Supply Input The maximum transient voltage (Note 1) Input Voltage VCONTROL Pin High Voltage Pin Power Dissipation and Thermal Characteristics: Maximum Power Dissipation @ TA = 70C Thermal Resistance Junction-to-Air Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 s) Rating Symbol VCC VCC VI VCONTROL HV PD RqJA TJ TJmax TSmax TLmax Value -0.3, +20 -0.3, +25 -0.3, +9 -0.3, VCONTROL MAX (Note 1) -0.3, +500 550 145 -40, +125 150 -65 to 150 300 Unit V V V V V mW C/W C C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. "VCONTROLMAX" is the pin clamp voltage
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NCP1605
Typical Electrical Characteristics Table(s)
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0C to +125C, unless otherwise specified) (Note 2) Symbol Gate Drive Section Trise Tfall ROH Isource ROL Isink Regulation Block VREF IEA GEA IBPin1 VCONTROL - VCONTROLMAX - VCONTROLMIN - D VCONTROLl VOUTL / VREF HOUTL / VREF IBOOST Shutdown Block ILEAKAGE VSTDWN Current Sourced by Pin 13 @ VPin14 = 2.3 V Pin 13 Threshold for Shutdown -500 2.375 - 2.500 500 2.625 nA V Voltage Reference Error Amplifier Current Capability Error Amplifier Gain Pin 1 Bias Current @ VPin1 = VREF Pin 2 Voltage: - @ VPin4 = 2 V - @ VPin4 = 3 V Ratio (VOUT Low Detect Threshold / VREF) (Note 5) Ratio (VOUT Low Detect Hysteresis / VREF) (Note 5) Pin 2 Source Current when (VOUT Low Detect) is activated - - 2.7 95.0 - 190 3.6 0.6 3.0 95.5 - 240 - - 3.3 96.0 0.5 290 % % mA 2.425 - 100 -500 2.500 20 200 - 2.575 - 300 500 V mA mS nA V Output Voltage Rise Time @ CL = 1 nF, from 1 V to 10 V Output Voltage Fall Time @ CL = 1 nF, from 10 V to 1 V Source Resistance @ IPin10 = 100 mA Source Current capability (@ VPin10 = 0 V) Sink Resistance @ IPin10 = 100 mA Sink Current Capability (@ VPin10 = 10 V) - - - - - - 40 20 15 500 7 800 - - 25 - 15 - ns ns W mA W mA Rating Min Typ Max Unit
Over and Under Voltage Protections VOVP VOVP / VREF VUVP / VREF IBPin14 Overvoltage Protection Threshold Ratio (VOVP / VREF) (Note 4) Ratio UVP threshold over VREF Pin 13 Bias Current: @ VPin14 = VOVP @ VPin14 = VUVP Ramp Control Pin 7 Source Current: IRAMP - 1.00 V IRAMP - 1.75 V IRAMP - 2.50 V Vcl_ff VCLCRM RCT @ VPin4 = 1.00 V @ VPin4 = 1.75 V @ VPin4 = 2.50 V Pin 7 Clamp Voltage @ VPin4 = VPin2 = 2 V and VPin6 = 0 V Pin 7 Clamp Voltage @ VPin4 = 0 V, VPin2 = 2 V and VPin6 = 1 V Ratio (Pin 7 Clamp Voltage / (Pin 7 Charge Current) (VCLCRM / IRAMP) @ VPin6 = 0 V and - VPin4 = 1.00 V - VPin4 = 1.75 V - VPin4 = 2.50 V - - - 16.7 5.4 2.7 - - - 54 156 313 - 0.9 60 182 370 5 1 69 214 428 - 1.1 V V kW mA -500 -500 - - 500 500 2.425 99.5 8 2.500 100.0 12 2.575 100.5 16 V % % nA
2. The maximum transient voltage with a corresponding maximum transient current at 100 mA. The maximum transient power handling capability must be observed as well. 3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit characterization has been performed. 4. Not tested; guaranteed by characterization 5. Not tested; guaranteed by design
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NCP1605
Typical Electrical Characteristics Table(s)
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0C to +125C, unless otherwise specified) (Note 2) Symbol TONMIN CINT VINIT IRAMP_SINK Delay (VPin7 > 5 V) to (DRV low) Average Pin 7 Internal Capacitance (VPin7 varying from 0 and 1 V) Guaranteed by design Maximum Pin 7 Voltage Allowing the Setting of the PWM Latch Pin 7 Sink Current (Drive low) @ VPin7 = 1 V Current Sense Pin Voltage, 100 mA being drawn from Pin 5 Current Sense Pin Voltage, 10 mA being drawn from Pin 5 Overcurrent Protection Threshold (Ipin5 > 250 mA) to (DRV low) Propagation Delay (Note 4) Ratio (IPin6/IPin5) @ IPin5 = 10 mA Ratio (IPin6/IPin5) @ IPin5 = 200 mA Pin 6 Comparator Threshold Delay from (VPin6 < VZCD) to (DRV high) Rating Min - - - - Typ 90 15 50 10 Max 200 25 90 - Unit ns pF mV mA
Current Sense Block Off100 Off10 IMAX TOCP KCS10 KCS200 VZCD TZCD Standby Input VSTBY HSTBY Standby Mode Threshold (VPin1 falling) Hysteresis for Standby Mode Detection 280 25 99 310 30 100 340 50 101 mV mV % -20 3 230 - 99 98 50 - 0 8 250 100 108 101 100 120 20 13 265 200 117 103 200 240 mV mV mA ns % % mV ns
VSKIPOUT / VOUTL Ratio (Pin 4 Voltage to terminate a SKIP period) over the (VOUT Low Detect Threshold) (Note 5) Oscillator / Synchronization Block Icharge Idisch Vsync_H Vsync_L Swing Tsync_min pfcOK / REF5V VpfcOKL VpfcOKH Pin 12 Voltage @ VPin13 = 5 V, 250 mA being sunk by Pin 12 Pin 12 Voltage @ VPin13 = 0 V and VPin3 = 5 V, with a 250 mA sourced by Pin 12 Pin 12 Voltage @ VPin13 = 0 V and VPin3 = 5 V, with a 5 mA sourced by Pin 12 Current Capability Oscillator Charge Current Oscillator Discharge Current Comparator Upper Threshold Comparator Lower Threshold Comparator Swing (Vsync_H - Vsync_L) Minimum Synchronization Pulse Width for Detection
90 90 - - 0.9 -
100 100 3 2 1 -
110 110 - - 1.1 500
mA mA V V V ns
- 4.7 4.5 5
60 5.0 5.0 10
120 5.3 5.3 -
mV V
Icap_ref
mA
Brown-Out Detection Block VBOH VBOL IBBO Thermal Shutdown TLIMIT Thermal Shutdown Threshold - 155 - C Brown-Out Comparator Threshold (VPin2 rising) Brown-Out Comparator Threshold (VPin2 falling) Pin 6 Bias Current @ VPin2 = 0.5 V and 1 V 0.9 0.45 -500 1.0 0.50 - 1.1 0.55 500 V V nA
2. The maximum transient voltage with a corresponding maximum transient current at 100 mA. The maximum transient power handling capability must be observed as well. 3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit characterization has been performed. 4. Not tested; guaranteed by characterization 5. Not tested; guaranteed by design
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NCP1605
Typical Electrical Characteristics Table(s)
(Conditions: VCC = 16 V, VHV = 50 V, VPin2 = 2 V, VPin13 = 0 V, TJ from 0C to +125C, unless otherwise specified) (Note 2) Symbol HTEMP Thermal Shutdown Hysteresis Rating Min - Typ 15 Max - Unit C
VCC UNDERVOLTAGE Lockout Section VCCON VCCOFF HUVLO VCCSTUP HLATCHOFF VCCRST Turn on Threshold Level, VCC Raising Up Minimum Operating Voltage after Turn-on Difference (VCCON - VCCOFF) VCC Threshold below which the Startup Current Source Turns on Difference (VCCOFF - VCCSTUP) VCC Level at which the Logic Resets 14 8 5 5.5 0.6 2 15 9 6 7.0 2.0 4 16 10 - 8.0 - 5 V V V V V V
Internal STARTUP Current Source IC1_hv IC1_Vcc IC2 High-Voltage Current Source (sunk by Pin 16), VCC = 13.5 V Startup Charge Current flowing out of the VCC Pin, VCC = 13.5 V High-Voltage Current Source, VCC = 0 V 5 5 - 12 12 0.5 20 20 1.0 mA mA mA
Device Consumption Icc_op1 Icc_op2 Icc_OFF Icc_latchOFF Power Supply Current: Operating (@ VCC = 16 V, no load, no switching) Operating (@ VCC = 16 V, no load, switching) Off Mode (@ VCC = 16 V, Pin 6 grounded) Latched-Off Mode (@ VCC = 13.5 V and VPin13 = 5 V) - 2.0 310 310 2.5 3.5 570 550 5 7 780 750 mA mA mA mA
2. The maximum transient voltage with a corresponding maximum transient current at 100 mA. The maximum transient power handling capability must be observed as well. 3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit characterization has been performed. 4. Not tested; guaranteed by characterization 5. Not tested; guaranteed by design
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NCP1605
PIN FUNCTION DESCRIPTION
Pin Number 1 Name STBY Function An external signal (typically, a portion of the feedback signal of the downstream converter or a filtered portion of the SMPS drive pulses) should be applied to Pin 1. When the Pin 3 voltage goes below 300 mV, the circuit enters a burst mode operation where the bulk voltage varies between the regulation voltage and 95.5% of this level. Apply a portion of the averaged input voltage to detect brown-out conditions. If VPin2 is lower than 0.5 V, the circuit stops pulsing until VPin2 exceeds 1 V (0.5 V hysteresis). Ground Pin 6 to disable the part. The error amplifier output is available on this Pin. The capacitor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios. Pin 3 is grounded when the circuit is off so that when it starts operation, the power increases slowly (soft-start). This pin receives a portion of the pre-converter output voltage. This information is used for the regulation and the "output low" detection (VOUTL) that drastically speed up the loop response when the output voltage drops below 95.5% of the wished level. This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the maximum coil current and detect the core reset (coil demagnetization). This pin sources the Pin 5 current. Place a resistor between Pin 6 and ground to build the voltage proportional to the coil current and detect the core reset. The impedance between Pin 6 and ground should not exceed 3 times that of the Pin 5 to ground. You can further apply the voltage from an auxiliary winding to improve the valley detection of the MOSFET drain source voltage. The circuit controls the power switch on-time by comparing the Pin 7 ramp to an internal voltage ("Vton") derived from the regulation block and the sensed "dcycle" (relative duration of the current cycle over the corresponding switching period). Pin 7 sources a current proportional to the squared output voltage to allow the Follower Boost operation (optional) where the PFC output voltage stabilizes at a level that varies linearly versus the ac line amplitude. This technique reduces the difference between the output and input voltages, to optimize the boost efficiency and minimize the size and cost of the PFC stage Connect a capacitor or apply a synchronization signal to this pin to set the switching frequency. If the coil current cycle is longer than the selected switching period, the circuit delays the next cycle until the core is reset. Hence, the PFC stage can operate in CRM in the most stressful conditions. Connect this pin to the pre-converter ground. The high current capability of the totem pole gate drive (+0.5/-0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs. This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 15 V and turns off when VCC goes below 9 V (typical values). After startup, the operating range is 10 V up to 20 V. The Pin 12 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low otherwise. This signal serves to "inform" the downstream converter that the PFC stage is ready and that hence, it can start operation. Apply a voltage higher than 2.5 V on Pin 13 to permanently shutdown the circuit. This pin can be used to monitor the voltage across a thermistor in order to protect the application from an excessive heating and/or to detect an overvoltage condition. To resume operation, it is necessary to decrease the circuit VCC below VCCRST (4 V typically) by for instance, unplugging the PFC stage and replugging it after VCC is discharged. The circuit turns off when VPin14 goes below 480 mV (UVP) and disables the drive as long as the pin voltage exceeds 2.5 V (OVP). Creepage distance. Connect Pin 16 to the bulk capacitor. The internal startup current source placed between Pin 16 and the VCC terminal, charges the VCC capacitor at startup.
2
Brown-Out / Inhibition VCONTROL / Soft-Start
3
4
Feedback
5 6
Current Sense Input Current Sense Output
7
Ct (Ramp)
8
Oscillator / synchronization GND Drive VCC PfcOK / REF5V
9 10 11 12
13
STDWN
14 15 16
OVP / UVP NC HV
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NCP1605
2.59 2.57 2.55 2.53 2.51 2.49 2.47 2.45 2.43 2.41 -40 -15 10 35 60 85 110 240 235 -40 IREF, (mA) VREF, (V) 260 255 250 245 265
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 2. Reference Voltage vs. Temperature
2.60 103 102 VOVP/VREF, (%) 101 100 99 98 97 -40
Figure 3. Reference Current vs. Temperature
2.56
VOVP, (V)
2.52
2.48
2.44 2.40 -40
-15
10
35
60
85
110
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 4. Overvoltage Threshold vs. Temperature
Figure 5. Ratio Overvoltage Threshold Overvoltage Reference vs. Temperature
2.61
2.56 VSTDWN, (V)
2.51
2.46
2.41
2.36 -40
-15
10 35 60 85 TJ, JUNCTION TEMPERATURE (C)
110
Figure 6. Shutdown Threshold vs. Temperature
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NCP1605
0.6 0.5 0.4
15.16 VUVPVREF, (%) -15 10 35 60 85 110
VUVP, (V)
13.12
0.3 0.2 0.1 0
11.08
9.04
-40
7 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 7. Undervoltage Protection Threshold vs. Temperature
15.4 9.7 9.4 9.1 VCCOFF, (V) VCCON, (V) 14.8 8.8 8.5 8.2 7.9 -40
Figure 8. Ratio (VUVP/VREF) vs. Temperature
15.1
14.5
14.2
13.9 -40
-15
10
35
60
85
110
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 9. VCC Turn on Threshold vs. Temperature (VCC Raising Up)
6.7
8.8 8.3
Figure 10. VCC Minimum Operating Voltage After Turn On
6.4 VCCSTUP, (V) -15 10 35 60 85 110
7.8 7.3 6.8 6.3 5.8 5.3
HUVLO, (V)
6.1
5.8
5.5
5.2 -40
4.8 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 11. Difference (VCCON - VCCOFF) vs. Temperature
Figure 12. VCC Threshold Below which the Startup Current Source Turns on vs. Temperature
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NCP1605
4 3.5 3 HLATCHOFF, (V) 2.5 2 1.5 1 0.5 -40 1 0 -40 VCCRST, (V) -15 10 35 60 85 110 6 5 4 3 2
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 13. Difference (VCCOFF-VCCSTUP) vs. Temperature
20 18 16 14 12 10 8 6 4 -40 -15 10 35 60 85 110 TJ, JUNCTION TEMPERATURE (C) IC1_VOFF, (mA) IC1_HV, (mA) 20 18 16 14 12 10 8 6 4 -40
Figure 14. VCC Level Below Which the Logic Resets vs. Temperature
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
Figure 15. High-Voltage Current Source (Sunk by Pin 16) vs. Temperature (@ VCC = 13.5 V)
1.2 90 80 HV_LEAKAGE, (mA) 0.9 IC2, (mA) 70 60 50 40 30 20 10 0 -40 -15 10 35 60 85 110 TJ, JUNCTION TEMPERATURE (C) 0
Figure 16. Startup Charge Current Flowing Out of the VCC Pin vs. Temperature (@ VCC = 13.5 V)
0.6
0.3
-40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
Figure 17. High-Voltage Current Source vs. Temperature (@ VCC = 0 V)
Figure 18. Pin 16 Leakage Current vs. Temperature (@ VPIN16 = 500 V and VCC = 16 V)
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NCP1605
24 22 IEA_SOURCE, (mA) 20 18 16 14 12 -40 IEA_SINK, (mA) -15 10 35 60 85 110 -12 -14 -16 -18 -20 -22 -24 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 19. Source Current Capability of the Error Amplifier vs. Temperature
300 260 220 GEA, (mS) 180 140 100 60 -40 150 100 50 0 -50 -100
Figure 20. Sink Current Capability of the Error Amplifier vs. Temperature
IBPIN4, (nA) -15 10 35 60 85 110
-150 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 21. Error Amplifier Gain vs. Temperature
Figure 22. Feedback Pin Bias Current vs. Temperature (@ VPIN4 = VREF)
3.3 3.2 D(VCONTROL), (V) 3.1 3 2.9 2.8 2.7 2.6
3.9 3.8 VCONTROLMAX, (V) 3.7 3.6 3.5 3.4 3.3 3.2 -40
-15
10
35
60
85
110
-40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 23. VCONTROL Maximum Voltage vs. Temperature
Figure 24. VCONTROL Maximum Swing (DVCONTROL) vs. Temperature
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NCP1605
95.9 95.8 95.7 VOUTL/VREF, (%) IBOOST, (mA) -15 10 35 60 85 110 95.6 95.5 95.4 95.3 95.2 95.1 -40 TJ, JUNCTION TEMPERATURE (C) 270 260 250 240 230 220 210 200 190 -40 -15 10 35 60 85 110 TJ, JUNCTION TEMPERATURE (C)
Figure 25. Ratio (VOUT Low Detect Threshold) / VREF vs. Temperature
110 105 ICHARGE, (mA) 100 95 90 85 80 -40
Figure 26. Pin 3 Source Current when (VOUT Low Detect Threshold) is Activated vs. Temperature
110 105 100 95 90 85 80 -40
-15
10
35
60
85
110
IDISCH, (mA)
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 27. Oscillator Charge Current vs. Temperature
1.01
150 125 100 75 50 25 0 -40
Figure 28. Oscillator Discharge Current vs. Temperature
0.99 pfcOK_L (mV) -15 10 35 60 85 110 SWING, (V)
0.97
0.95
0.93
0.91 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 29. Oscillator Swing vs. Temperature
Figure 30. pfcOK Pin Low Level Voltage vs. Temperature
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NCP1605
5.5 5
5.3 ICC_OP1, (mA) pfcOK_H, (V)
4
5.1
3
4.9
2
4.7
1
4.5 -40
-15
10
35
60
85
110
0 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 31. pfcOK Pin High Level Voltage vs. Temperature (250 mA Load)
6 800
Figure 32. Operating Consumption vs. Temperature (VCC = 16 V, No Load, No Switching)
5 ICC_OP2, (mA) ICCOFF, (mA) -15 10 35 60 85 110
700
4
600
3
500
2 1 -40
400
300 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 33. Operating Consumption vs. Temperature (VCC = 16 V, No Load, Switching)
800
Figure 34. Off Mode Consumption vs. Temperature (VCC = 16 V, Pin 2 Grounded)
700 ICCSTDOWN, (mA)
600
500
400
300 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
Figure 35. Shutdown Mode Consumption vs. Temperature (VCC = 16 V, Pin 2 GND)
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NCP1605
1.1 0.6
1.05 VCBOH, (V) VCBOL, (V) -40 -15 10 35 60 85 110
0.55
1
0.5
0.95
0.45
0.9 TJ, JUNCTION TEMPERATURE (C)
0.4 -40 -15 10 35 60 85 110 TJ, JUNCTION TEMPERATURE (C)
Figure 36. Brown-Out Upper Threshold vs. Temperature
14 12 10 OFF100, (mV) OFF10, (mV) 8 6 4 2 0 -2 -40 -15 10 35 60 85 110 TJ, JUNCTION TEMPERATURE (C) 4 2 -40 10 8 6 14 12
Figure 37. Brown-Out Lower Threshold vs. Temperature
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
Figure 38. Current Sense Pin Voltage vs. Temperature (100 mA Being Drawn from Pin 5)
68 66 IRAMP_1.00 V, (mA) IRAMP_1.75 V, (mA) 64 62 60 58 56 54 52 -40 -15 10 35 60 85 110 TJ, JUNCTION TEMPERATURE (C) 208 203 198 193 188 183 178 173 168
Figure 39. Current Sense Pin Voltage vs. Temperature (10 mA Being Drawn from Pin 5)
163 158 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
Figure 40. Pin 7 Source Current @ VPIN4 = 1.0 V vs. Temperature
Figure 41. Pin 7 Source Current @ VPIN4 = 1.75 V vs. Temperature
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NCP1605
415 405 395 IRAMP_2.50 V, (mA) 385 375 365 355 345 335 325 -40 -15 10 35 60 85 110 3 -40 -15 10 35 60 85 110 4 RCT (kW) TJ, JUNCTION TEMPERATURE (C) 6 7 8
5
TJ, JUNCTION TEMPERATURE (C)
Figure 42. Pin 7 Source Current @ VPIN4 = 2.5 V vs. Temperature
112
200 180
Figure 43. Ratio Pin 7 Clamp Voltage / (Pin 7 Charge Current) that is (VCLCRM / IRAMP) @ VPIN6 = 0 V and VPIN4 = 1.75 V
110 VZCD, (mV) -15 10 35 60 85 110 Kcs10, (%)
160 140 120 100 80 60
108
106
104 -40
40 -40
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 44. Ratio (IPIN6 / IPIN5) @ IPIN5 = 10 mA vs. Temperature
220 200 180 160 140 120 100 80 60 40 -40 VSKIPH, (V) TZCD, (ns) 310 300 290 280 270 -15 10 35 60 85 110 260 -40 340 330 320
Figure 45. Pin 6 Comparator Threshold vs. Temperature
-15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 46. Delay from (ZCD Pin Low) to (DRV High) vs. Temperature
Figure 47. Skip Cycle Threshold (VPIN1 Falling) vs. Temperature
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NCP1605
180 160 140 120 tOMIN, (ns) ROH, (W) -15 10 35 60 85 110 100 80 60 40 20 0 -40 26 24 22 20 18 16 14 12 10 8 -40 -15 10 35 60 85 110
TJ, JUNCTION TEMPERATURE (C)
TJ, JUNCTION TEMPERATURE (C)
Figure 48. Minimum On-Time vs. Temperature
Figure 49. Gate Drive Source Resistance vs. Temperature
16 14 12 ROL, (W) 10 8 6 4 2 -40
-15 10 35 60 85 TJ, JUNCTION TEMPERATURE (C)
110
Figure 50. Gate Drive Sink Resistance vs. Temperature
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NCP1605
Vout Low Detect 95.5% Vref + - VoutL
200 mA
All the RS latches are RESET dominant UVLO
HVCS_ON HV UVLOs Latch Reset
FB
pfcOK Error Amplifier VSTBY - + 20 mA Vref V/I Iout FLAG1
VDD
Internal Thermal Shutdown TSD
UVLO (VccVcontrol
OFF SKIP FLAG1 LSTBY S Q R VoutL pfcOK 3V R 2.R VREGUL SKIP DT VREGUL
BO_NOK STDWN
FAULT Management
OVP Vton processing circuitry
Vref VDD Iref Regul VCC
STBY +
- + VSTBY 300 mV
Vt(on) - + Ich=K.Iout.Iout Ct outON CLK Oscillator / Synchronization Block DT Ics > 250 mA Ics - + 100 mV OCP Q R Dead-time Detection Latch S ZCD OVP OCP PWM Comparator OFF SKIP outON RR R Q R PWM S Latch VCC Output Buffer
Drv
BO / Stdwn
1 V / 0.5 V
- +
BO_NOK
50 mV
- + outON
Ct_OK
OSC / SYNC
Ics CSin
CSout
+ -
ZCD REF5V
pfcOK - + + - UVP FLAG1 OFF OVP Vref - + stdwn S R VccpfcOK / REF5V
OVP
12% Vref
GND
Vovp = Vref
Figure 51. Block Diagram http://onsemi.com
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NCP1605
Detailed Operating Description
Introduction
The NCP1605 is a PFC driver designed to operate in fixed frequency, Discontinuous Conduction Mode (DCM). In the most stressful conditions, Critical Conduction Mode (CRM) can be achieved without power factor degradation and the circuit could be viewed as a CRM controller with a frequency clamp (given by the oscillator). Finally, the NCP1605 tends to give the best of both modes without their respective drawbacks. Furthermore, the circuit incorporates protection features for a rugged operation together with some special circuitry to lower the power consumed by the PFC stage in no load conditions. More generally, the NCP1605 functions make it the ideal candidate in systems where cost-effectiveness, reliability, low standby power and high power factor are the key parameters: * Compactness and Flexibility: the controller requires few external components while offering a large variety of functions. Depending on the selected coil and oscillator frequency you select, the circuit can: 1. Mostly operate in CRM and use the oscillator as a frequency clamp. 2. Mostly operate in fixed frequency mode and only run in CRM at high load and low line. 3. Permanently operate in fixed frequency mode DCM. In all cases, the circuit provides near-unity power factor. Skip-cycle capability for low power standby: among other applications, the circuit targets power supply where the PFC stage must keep alive even in standby. A continuous flow of pulses is not compatible with no-load standby power requirements. Instead, the controller slices the switching pattern in bunch of pulses to drastically reduce the overall losses. The skip cycle operation is initiated by applying to Pin 1, a signal that goes below 300 mV in standby. Typically, this signal is drawn from the feedback of the downstream converter. Startup Current Source and large VCC range: meeting low standby power specifications represents a difficult exercise when the controller requires an external, lossy resistor connected to the bulk capacitor. The controller disables the high-voltage current source after startup which no longer hampers the consumption in no-load situations. In addition, the large VCC range (10 V to 20 V after startup), highly eases the circuit biasing. Fast Line / Load Transient Compensation: given the low bandwidth of the regulation block, the output voltage of PFC stages may exhibit excessive over and undershoots because of abrupt load or input voltage variations (e.g. at startup). If the output voltage is too far from the regulation level:
- The NCP1605 disables the drive to stop delivering power as long as the output voltage exceeds the Overvoltage Protection (OVP) level. - The NCP1605 drastically speeds up the regulation loop when the output voltage is below 95.5% of its regulation level. This function is allowed only after the PFC stage has started up not to eliminate the soft-start effect. PFC OK: the circuit detects when the circuit is in normal situation or if on the contrary, it is in a startup or fault condition. In the first case, Pin 12 is in high state and low otherwise. Pin 12 serves to control the downstream converter operation in response to the PFC state. Safety Protections: the NCP1605 permanently monitors the input and output voltages, the coil current and the die temperature to protect the system from possible over-stresses and make the PFC stage extremely robust and reliable. In addition to the aforementioned OVP protection, one can list: - Maximum Current Limit and Zero Current Detection: the circuit permanently senses the coil current and immediately turns off the power switch if it is higher than the set current limit. It also prevents any turn on of the power switch as long as some current flows through the coil, to ensure operation in DCM. This feature also protects the MOSFET from the excessive stress that could result from the large in-rush currents that occurs during the startup phases. - Undervoltage Protection: the circuit turns off when it detects that the output voltage goes below 12% of the OVP level (typically). This feature protects the PFC stage from starting operation in case of too low ac line conditions or in case of a failure in the OVP monitoring network (e.g., bad connection). - Brown-Out Detection: the circuit detects too low ac line conditions and stop operating in this case. This protection protects the PFC stage from the excessive stress that could damage it in such conditions. - Thermal Shutdown: an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 150C typically. The circuit resumes operation once the temperature drops below about 100C (50C hysteresis). Output Stage Totem Pole: the NCP1605 incorporates a -0.5 A / +0.8 A gate driver to efficiently drive most TO220 or TO247 power MOSFETs.
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NCP1605
NCP1605 Operation Modes
*
* *
Like the NCP1601, the NCP1605: Features a current sense block that prevents the PFC stage from operating in CCM: as long as the coil current is not null, the power switch is not allowed to turn on. Hence the circuit can only operate in either Fixed Frequency DCM or CRM. Features the capability to exhibit near-unity power factor while operating in any type of Discontinuous Conduction Mode operation: DCM or CRM. Auto adapts: if there is some current flowing through the coil when the clock occurs to initiate a new current cycle, the PFC stage enters CRM. On the other hand, if the clock occurs during dead-times, one obtains a fixed frequency operation DCM. Thanks to its special oscillator/synchronization arrangement, the circuit automatically enters the appropriate mode CRM or
DCM. It is worth noting that jumps between the CRM and modes cause absolutely no degradation: the input current keeps being properly shaped and there is no discontinuity in the power transfer. Given the dead-time presence, DCM needs a higher peak inductor current compared to CRM for the same delivered power. Hence, the coil is generally designed to have CRM at the most stressful conditions while DCM limits the switching frequency at lower load. The circuit can also transition within an ac line cycle so that: * CRM reduces the current stress around the sinusoid top. * DCM limits the frequency around the line zero crossing. This capability offers the best of each mode without the drawbacks. The way the circuit modulates the MOSFET on-time allows this facility.
Current Inductor Current, IL
Input Current, Iin
Time DCM Critical Mode DCM
Figure 52. DCM and CRM Operation Within a Sinusoid Cycle
The NCP1605 can jump from DCM to CRM within a sinusoid cycle (and vice versa) without any discontinuity in the current shaping or the power transfer.
NCP1605 On-time Modulation
Let's study the ac line current absorbed by the PFC boost. The initial inductor current of each switching cycle is always zero. The coil current ramps up when the MOSFET is on. The slope is (VIN/L) where L is the coil inductance. At the end of the on-time (t1), the coil demagnetization phase starts. The coil current ramps down until this sequence ends when it reaches zero. The duration of this phase is (t2). The system enters then the dead-time (t3) that lasts until the next clock is generated.
One can show (refer to NCP1601 data sheet) that the ac line current is given by:
Iin + Vin t1 (t1 ) t2) 2TL
(eq. 1)
Where T = (t1 + t2 + t3) is the switching period and VIN is the ac line rectified voltage. To the light of this equation, we immediately note that IIN is proportional to VIN if [t1(t1 + t2)/T] is a constant.
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NCP1605
Vin Iin L Vout Ipk t1 t2 T t3 Inductor Current
Time
Figure 53. PFC Boost Converter
Figure 54. Inductor Current in DCM
The NCP1605 operates in voltage mode. As portrayed by Figure 55, the MOSFET on time t1 is controlled by the signal Vton generated by the regulation block and the Pin 4 ramp as follows:
t1 + Cpin7 @ VTON Ipin7
(eq. 2)
Given the regulation low bandwidth of the PFC systems, (VCONTROL) and then (VREGUL) are slow varying signals. Hence, the (VTON * (t1 + t2)/T) term is substantially constant. Provided that in addition, (t1) is proportional to (VTON), equation (1) leads to: (Iin = k * Vin), where k is a constant. More exactly:
Iin + k @ Vin where : k + constant + Cpin7 @ VREGUL 120 m @ L @ (Vpin2) 2
(eq. 4)
The charge current that is sourced by Pin 7 [Ipin7 = 60 mA/V2 * (VPin4)2] is constant at a given input voltage (VPin4 is proportional to the output voltage). Cpin7 that is the capacitor connected between Pin 7 and ground is also a constant. Hence, the power factor correction is achieved when the VTON (t1 + t2)/T term is constant. The output of the regulation block (VCONTROL) is linearly changed into a signal (VREGUL) varying between 0 and 1 V. (VREGUL) is the voltage that is injected into the PWM section to modulate the MOSFET duty-cycle. However, like the NCP1601, the NCP1605 inserts some circuitry that processes (VREGUL) to form the signal (VTON) that is used in the PWM section instead of (VREGUL) (see Figure 56). (VTON) is modulated in response to the dead-time sensed during the precedent current cycles, that is, for a proper shaping of the ac line current (refer to NCP1601 data sheet). This modulation leads to:
VTON + T @ VREGUL t ) t2 or : VTON @ 1 + VREGUL t1 ) t2 T
(eq. 3)
The input current is then proportional to the input voltage. Hence, the ac line current is properly shaped. One can note that this analysis is also valid in the CRM case. This condition is just a particular case of this functioning where (t3 = 0), which leads to (t1 + t2 = T) and (VTON = VREGUL). That is why the NCP1605 automatically adapts to the conditions and jumps from DCM and CRM (and vice versa) without power factor degradation and without discontinuity in the power delivery. Remark: Like in the NCP1601, the "VTON processing circuit" is "informed" when there is an OVP condition, not to over-dimension VTON in that conditions. Otherwise, an OVP sequence would be viewed as a dead-time phase by the circuit and VTON would inappropriately increase to compensate it. Similarly, the "VTON processing circuit" is inhibited for a skip sequence not to over-dimension "VTON" in this case (refer to Figure 56).
timing capacitor saw-tooth PWM comparator + to PWM latch -
Ich PWM Comparator VREGUL Closed When Output Low Cramp Vton Turns Off MOSFET IN1 -> Vton during (t1+t2) -> 0 V during t3 (dead-time) -> Vton*(t1+t2)/T in average R1 + - C1 S1 OA1 Vton
S3
SKIP OFF OVP
S2 DT (high during dead-time)
Vton Ramp Voltage
Figure 56. VTON Processing Circuit
PWM Outtage
Figure 55. PWM Circuit and Timing Diagram
The integrator OA1 amplifies the error between VREGUL and IN1 so that in average, (VTON*(t1+t2)/T) equates VREGUL.
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NCP1605
350,00 300,00 250,00 Vin (V) 200,00 150,00 100,00 50,00 0,00 0 2 4 6 8 10 time (ms) 12 14 16 18 20 3,50 3,00 2,50 2,00 1,50 1,00 0,50 0,00
Figure 57. Input Voltage and On-time vs Time (example with FSW = 100 kHz, Pin =150 W, VAC = 230 V, L = 200 mH)
Regulation Block and Low Output Voltage Detection
A transconductance error amplifier with access to the inverting input and output is provided. It features a typical transconductance gain of 200 mS and a maximum capability of 20 mA. The output voltage of the PFC stage is typically scaled down by a resistors divider and monitored by the inverting input (feedback pin - Pin 4). The bias current is minimized (less than 500 nA) to allow the use of a high impedance feedback network. The output of the error amplifier is pinned out for external loop compensation (Pin 3). Typically a capacitor in the range of 100 nF, is applied between Pin 3 and ground, to set the regulation bandwidth below 20 Hz, as need in PFC applications.
Vout Low Detect 0.955*Vref FB Vref Vcontrol OVLflag1 OFF + VF 2R 3V R VREGUL + VF - + - + pfcOK 200 mA
The swing of the error amplifier output is limited within an accurate range: * It is forced above a voltage drop (VF) by some circuitry. * It is clamped not to exceed 3.0 V + the same VF voltage drop. Hence, VPin3 features a 3 V voltage swing. VPin3 is then offset down by (VF) and divided by three before it connects to the "VTON processing block" and the PWM section. Finally, the output of the regulation is a signal ("VREGUL" of the block diagram) that varies between 0 and 1 V.
VREGUL 1V
Error Amplifier 20 mA
0V VF 3 V + VF VCONTROL
Figure 58. Regulation Block
Figure 59. Correspondence between VCONTROL and VREGUL
Provided the low bandwidth of the regulation loop, sharp variations of the load, may result in excessive over and undershoots. Overshoots are limited by the Overvoltage Protection (see OVP section). To contain the undershoots, an internal comparator monitors the feedback (VPin4) and when VPin4 is lower than 95.5% of its nominal value, it connects a
200 mA current source to speed-up the charge of the compensation capacitor (Cpin3). Finally, it is like if the comparator multiplied the error amplifier gain by 10. One must note that this circuitry for undershoots limitation, is not enabled during the startup sequence of the PFC stage but only once the converter has stabilized (that is when the
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NCP1605
"pfcOK" signal of the block diagram, is high). This is because, at the beginning of operation, the Pin 3 capacitor must charge slowly and gradually for a soft-startup. Remark: As shown in block diagram, the circuitry for undershoots limitation is disabled as long as Pin 3 detects standby conditions (VPin3 < 300 mV). This is to suppress the risk of audible noise in standby thanks to the soft-start that softens the bursts.
On-Time Control for Maximum Power Adjustment
As aforementioned, the NCP1605 processes the error amplifier output voltage to form a signal (VTON) that is used by the PWM section to control the on-time. (VTON) compensates the relative weight of the dead-time sequences measured during the precedent current cycles. During the conduction time of the MOSFET, Pin 7 sources a current that is proportional to the square of the voltage applied to Pin 4 (feedback pin). Practically, as Pin 4 receives a portion of the output voltage (VOUT), IPin7 is proportional to the square of VOUT. The MOSFET turns off when the Pin 7 voltage exceeds VTON. Hence, the MOSFET on-time (t1) is given by:
t1 + Cpin7 VTON where k is a constant. k VOUT 2
Hence, one obtains the Follower Boost characteristics. The "Follower Boost" is an operation mode where the pre-converter output voltage stabilizes at a level that varies linearly versus the ac line amplitude. This technique aims at reducing the gap between the output and input voltages to optimize the boost efficiency and minimize the cost of the PFC stage (refer to the MC33260 data sheet for more information, at: http://www.onsemi.com/pub/Collateral/MC33260-D.PDF ). Remark: the timing capacitor applied to Pin 7 is discharged and maintained grounded when the drive is low. Furthermore, the circuit compares the Pin 7 voltage to an internal reference 50 mV and prevents the PWM latch from being set as long as VPin7 is higher than this low threshold. This is to guarantee that the timing capacitor is properly discharged before starting a new cycle.
Current Sense and Zero Current Detection
The coil current averaged over one switching period is:
V t (t1 ) t2) t ICOIL u T + IIN(t) + IN 1 T 2L
Where IIN(t) and VIN(t) are the instantaneous input current and voltage, respectively, t2 is the core reset time and T is the switching period. Hence, the instantaneous input power is given by the following equation:
Cpin7 VIN2 VTON (t1 ) t2) PIN(t) + VIN(t)IIN(t) + @ T 2 L k VOUT 2
The NCP1605 is designed to monitor a negative voltage proportional to the coil current. Practically, a current sense resistor (RCS) is inserted in the return path to generate a negative voltage proportional to the coil current (VCS). The circuit uses VCS for two functions: the limitation of the maximum coil current and the detection of the core reset (coil demagnetization). To do so, the circuit incorporates an operational amplifier that sources the current necessary to maintain the CS pin voltage null (refer to Figure 60). By inserting a resistor ROCP between the CS pin and RCS, we adjust the CS pin current as follows:
* [RCS ICOIL] ) [ROCP Ipin5] + Vpin5 [ 0
Which leads to:
R Ipin5 + CS ICOIL ROCP
As aforementioned, we have: VTON (t1 + t2)/T = VREGUL where VREGUL is the signal outputted by the regulation block. Hence, the average input power is:
t PIN u+ Cpin7 Vac 2 V 2 L k VOUT 2 REGUL
In other words, the Pin 5 current is proportional to the coil current. IPin5 is utilized as follows: * If IPin5 exceeds 250 mA, an overcurrent is detected and the PWM latch is reset. Hence, the maximum coil current is:
R (ICOIL)max + OCP 250 mA RCS
The maximum value of VREGUL being 1 V, the maximum power that can be delivered is:
t PIN u MAX + Cpin7 Vac 2 1V 2 L k VOUT2
To the light of the last equations, one can note that the PFC power capability is inversely proportional to the square of the output voltage. One sees that if the power demand is too high to keep the regulation, (VREGUL=1V) and the power delivery depends on the output voltage level that stabilizes to the following value:
VOUT + Cpin7 1 V V 2 L k h POUT ac
*
The propagation delay (Ipin5 higher than 250 mA) to (drive output low) is in the range of 100 ns, typically. The Pin 5 current is internally copied and sourced by Pin 6. Place a resistor (RPin6) between Pin 6 and ground to build a voltage proportional to the coil current. The circuit detects the core reset when VPin6 drops below 100 mV, typically. The Pin 6 voltage equating:
Vpin6 + Rpin6 @ Rcs @ ICOIL , Rcs
the coil current threshold for zero current detection is:
Where: * POUT is the output power. * And h is the efficiency.
ROCP 100 mV (ICOIL)zcd + 100 mV + @ (ICOIL)MAX + 400 W @ (ICOIL)MAX Rpin6 @ RCS Rpin6 @ 250 mA Rpin6
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NCP1605
Rdrv Rzcd Vin Icoil 6 EMI Filter Cin Vdd Current Mirror Vdd Ics Ics CSout 100 mV + - ZCD Vcc DRV 10 outON S LdT Q R L1 M1 Cbulk LOAD D1 Vout
output buffer
Vzcd Rocp CSin Rsense 5 Icoil Ics > 250 mA OCP
DT
OCP (RESET of the PWM latch)
Figure 60. Current Sense Block
The CS block performs the overcurrent protection and the zero current detection.
The propagation delay (VPin6 lower than 100 mV) to (drive output high) is in the range of 300 ns, typically.
* Is used to detect the dead-time sequences ("DT" high)
and hence, to process (VTON) from the error amplifier output (VCONTROL). In other words, this is an input of the on-time modulation block. Prevents the MOSFET from turning on as long as the "DT" and "ZCD" signals are low. This is the case as long as some current flows through the coil. This delaying action on the output stage tends to make the MOSFET turn on at the valley. To further optimize the valley switching, one can apply the voltage of an auxiliary winding to Pin 6 (CSOUT). The voltage is compared to an internal 100 mV reference, so that ZCD turns high only if (VPin6 < 100 mV).
The Zero Current Detection:
*
It is recommended to: 1. Keep ROCP equal to or lower than 5 kW 2. Choose RZCD as high as possible but not bigger than (3 x ROCP). This is to avoid that the Pin 6 leakage prevents a proper zero current detection. For instance, if ROCP is 2.2 kW, RZCD should not exceed 6.6 kW. 3. Place a resistor RDRV between the drive pin and Pin 6 to ease the circuit detection by creating some over-riding at the turn on instant. RDRV should be selected in the range of 3 times RZCD. For instance, if RZCD is 6.2 kW, a 22 kW resistor can be used for RDRV.
Overvoltage Protection
Remarks:
* A resistor can be placed between Pin 6 and ground to
increase the ZCD precision.
* It is worth highlighting that the circuit permanently
senses the coil current and that it prevents any turn on of the power switch as long as the core is not reset. This feature protects the MOSFET from the possible excessive stress it could suffer from, if it was allowed to turn on while a huge current flows through the coil. In particular, this scheme effectively protects the PFC stage during the startup phase when huge in-rush currents charge the output capacitor. In addition this detection method does not require any auxiliary winding. A simple coil can then be used in the PFC stage.
While PFC circuits often use one single pin for both the Overvoltage Protection (OVP) and the feedback, the NCP1605 dedicates one specific pin for the undervoltage and overvoltage protections. The NCP1605 configuration allows the implementation of two separate feedback networks (see Figure 62): - One for regulation applied to Pin 4. - Another one for the OVP function.
*
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NCP1605
Vout (bulk voltage) Vout (bulk voltage)
Rout1
1 16 2 15 3 14 FB 4 13 5 12 6 11 7 10 8 9
HV OVP Rout1 FB
1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9
HV Rovp1 OVP
Rout3
Rout2
Rout2
Rovp2
Figure 61. Configuration with One Feedback Network for Both OVP and Regulation
Figure 62. Configuration with Two Separate Feedback Networks
The double feedback configuration offers some up-graded safety level as it protects the PFC stage even if there is a failure of one of the two feedback arrangements. However, if wished, one single feedback arrangement is possible as portrayed by Figure 61. The regulation and OVP blocks having the same reference voltage, the resistance ratio Rout2 over Rout3 adjusts the OVP threshold. More specifically, The bulk regulation voltage is:
Vout + Rout1 ) Rout2 ) Rout3 @ Vref Rout2 ) Rout3 Rout1 ) Rout2 ) Rout3 @ Vref Rout2 R Vovp + 1 ) out3 Vout Rout2
The OVP level is:
Vovp +
The ratio OVP level over regulation level is:
For instance, (VOVP = 105% * Vout) leads to the following constraint: (Rout3 = 5% * Rout2). As soon and as long as the circuit detects that the output voltage exceeds the OVP level, the power switch is turned off to stop the power delivery. Remark: Like in the NCP1601, the "VTON processing circuit" is "informed" when there is an OVP condition, not to over-dimension VTON in that conditions. Otherwise, an OVP sequence would be viewed as a dead-time phase by the circuit and VTON would inappropriately increase to compensate it (refer to Figure 56).
PfcOK / REF5V Signal
The startup phase is detected by the latch "LSTUP" of the block diagram. "LSTUP" is set during each "off" phase so that its output ("STUP") is high when the circuit enters an active phase. The latch is reset when the error amplifier stops charging its output capacitor, that is, when the output voltage of the PFC stage has reached its desired regulation level. At that moment, "STUP" falls down to indicate the end of the startup phase. * In case of a condition preventing the circuit from operating properly, i.e., during the VCC charge by the high voltage startup current source, in a Brown-out case or when one of the following major faults turns off the circuit: - Incorrect feeding of the circuit ("UVLO" high when VCCStandby Management
The NCP1605 can communicate with the downstream converter. The signal "pfcOK/REF5V is high (5 V) when the PFC stage is in normal operation (its output voltage is stabilized at the nominal level) and low otherwise. More specifically, "pfcOK/REF5V" is low: * During the PFC stage startup, that is, as long as the output voltage has not yet stabilized at the right level.
The NCP1605 automatically skips switching cycles when the power demand drops below a given level. This is accomplished by monitoring the Pin 1 voltage that must receive a voltage below 300 mV in light load conditions. Practically, a portion of the feedback signal of the downstream converter (or some other signal able to indicate that the power demand is low) should be applied to Pin 1.
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NCP1605
PFC stage Rectified AC line 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 NCP1605 VCC + + SMPS controller downstream converter
Standby Input Voltage
C
Feed-back of the downstream converter
Figure 63. Signal for Standby Detection
In normal operation, the circuit controls the continuous absorption of the line current necessary for matching the load power demand. When the voltage applied to Pin 1 goes below 300 mV: * The output pulses are blanked and Pin 3 ("VCONTROL") is grounded. * The output of the PFC stage being not fed any more, it drops. When the output voltage goes below 95.5% of the regulation level, the circuit resumes operation until "FLAG1" becomes low (what means that the output voltage has exceeded the regulation level). * At that moment, if VPin1 is still below 300 mV, a new skipping phase starts.
In other words, instead of continuously providing the output with a small amount of power, the circuit operates from time to time at a higher power level. As an example and to make it simple, instead of continuously supplying 1% of PMAX, the circuit can provide the load with 10% of PMAX for 10% of the time. The IC enters the so-called skip cycle mode, also named controlled burst operation. This burst operation is much more efficient compared to a continuous power flow as it drastically reduces the number of pulsations and therefore the switching losses associated to them.
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NCP1605
VPin1 300 mV
VCONTROL
VOUT 95.5% of the Regulation Level
SKIP
VOUTL
Drive
Figure 64. Standby Management Remark:
* Skip cycle is not allowed during the PFC startup phase *
to avoid that it interferes with the soft-start. That is why, skip cycle is enabled only when "pfcOK" is high. Each working phase of the burst mode starts smoothly as Pin 3 is grounded at the beginning of it. This soft-start capability is effective to avoid the audible noise that could possibly result from such a burst operation. The circuit leaves the standby mode when the output voltage goes below 95.5% of its regulation level and VPin1 is above 330 mV (300 mV + 30 mV hysteresis).
*
Oscillator / Synchronization Section
The oscillator generates the clock signal to set the PWM latch and turn the MOSFET on. The oscillator frequency is set by the capacitor that is applied to Pin 8. Typically, 820 pF force about 60 kHz. The maximum allowable oscillator frequency is 250 kHz. The clock frequency can also be driven by an external synchronization signal. This block contains two main parts (refer to Figure 66): * The arrangement that consists of charging/discharging current sources, a switch and a comparator. When used in oscillator mode, a capacitor is connected between Pin 8 and ground. A current source (100 mA) charges the Pin 8 capacitor until its voltage exceeds VoscH. At that moment, the comparator ("COMP_OSC") turns high and activates the discharge current source (200 mA). As a consequence, Pin 8 actually sinks 100 mA that discharge the oscillator capacitor to VoscL. At that moment, the comparator turns low and initiates a new charge phase. If the circuit is to be externally triggered, the synchronization signal must cross VoscL and VoscH to
properly turn on and off the "COMP_OSC" comparator. Also the synchronization signal must be low impedance enough not to be distorted by the Pin 8 source and sink currents. * The "storing circuitry" that contains a latch and some gates. The raising edge of the "COMP_OSC" output sets the "CLOCK Generation" latch to turn high the "CLK" signal. If the timing capacitor of Pin 7 is properly discharged (VPin4 <50 mV leading to "CTOK" high), the PWM block is ready for a new cycle and "CLK" can force the signal "VSET" in high state. As a consequence, the PWM latch sets. In addition, "VSET" resets the "CLOCK Generation" latch to make it ready for the next oscillator cycle. The two inverters of Figure 66, simply generate some delay to ensure that "VSET" keeps high long enough to set the PWM latch and reset the "CLOCK Generation" latch (longer delay than that produced by the two gates, may actually be necessary). The oscillator / Synchronization block is designed to set the switching frequency. However, the coil current can possibly be non zero at the end of a clock period and the circuit would enter Continuous Conduction Mode (CCM) if the MOSFET turned on in that moment. In order to prevent CCM, the "storing circuitry" of the oscillator / synchronization block, memorizes the "COMP_OSC" rising edge (thanks to the "CLOCK Generation" latch) and delays the next MOSFET conduction time until the coil current has totally vanished (that is until the signal "DT" is high - "DT" is generated by the current sense block so that it is high during the dead-time and low otherwise). In other words, CRM operation is obtained (refer to Figure 65).
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NCP1605
delay Clock Clock Edge Set Signal Inductor Current Discontinuous Mode Critical Mode Time 100 mA Osc/Sync 200 mA COMP_OSC + - R CLOCK Generation Latch Q S Ct_OK CLK (PWM latch SET input)
DT ("DT" is high during the dead-time)
VOSCH/VOSCL
Figure 65. Oscillator Timing Diagram
Figure 66. Oscillator / Synchronization Block
HV 16 15 mA / 0 HVCS_ON 15 V / 7 V + - VCC 10 + 9V - + UVLO GND 9
HV
Cvcc
Auxiliary Winding
(When high, "UVLO" indicates that the circuit is not properly fed and it sets the Fault latch to turn off the circuit)
Figure 67. The Current Source brings VCC above 15 V and then Turns Off
Startup Sequence / VCC Management
At the moment when the PFC stage is plugged to the mains outlet, the internal current source starts charging the VCC capacitor. More generally, the startup current source is enabled whenever VCC drops below VCCSTUP (7 V, typically). When VCC exceeds the VCCON level (typically 15 V), the current source turns off and the circuit starts pulsing. The energy stored by the VCC capacitor serves to feed the controller and some auxiliary supply must take over before VCC drops below VCCOFF (9 V, typically), that is, the level below which the circuit stops pulsing. Hence, the circuit starts operating when the VCC voltage exceeds 15 V and stops pulsing when VCC drops below 9 V. The 6 V hysteresis prevents erratic operation as the VCC crosses the 15 V threshold. Figure 67 shows the internal arrangement of this structure. One can note that the startup current source is on
during the VCC charging phase and off for the rest of the time. Hence, it spends no power during the PFC stage operation and in particular, in light load conditions. That is why the NCP1605 helps meet the most stringent standby requirements.
Remarks:
* Some circuitry (not represented in Figure 67) limits
the HV pin current below 1 mA if the VCC voltage is nearly below 1 V. This protects the circuit when the VCC pin is accidentally grounded. The full current capability (around 15 mA) is obtained when VCC exceeds about 1 V. The circuit is also kept off when the startup current source is on to make a clear distinction between the VCC charge phase and the operating sequence (refer to "HVCS_ON" signal on block diagram).
*
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NCP1605
Brown-Out Detection
The brown-out pin receives a portion of the input voltage (VIN). As VIN is a rectified sinusoid, a capacitor must integrate the ac line ripple so that a voltage proportional to the average value of (VIN) is applied to the brown-out pin. The brown-out block detects too low input voltage conditions. A hysteresis comparator monitors the Pin 2 voltage. Before operation, the PFC stage is off and the input bridge acts as a peak detector. Hence, the voltage applied to Pin 2 is:
Rbo2 Vpin2 + 2 Vac . Rbo1 ) Rbo2
Vpin2 +
Rbo2 2 2 Vac , p Rbo1 ) Rbo2
i.e., about 64% of the previous value. Therefore, the same line magnitude leads to a VPin2 voltage that is 36% lower when the PFC is working than when it is off (refer to Figure 69). That is why the NCP1605 features a 50% hysteresis (VBOL = 50% VBOH). When the circuit starts operation, the input voltage equates the ac line peak.
Hence, the initial threshold of the Brown-Out comparator, must be the upper one (VBO = VBOH = 1 V when the NCP1605 leaves the off mode).
After the PFC stage has started operation, the input voltage becomes a rectified sinusoid and the voltage applied to Pin 2 is:
Vin Ac line Rbo1 Cin BO 1 V / 0.5 V BO_NOK 200 RCS Cbo2 Rbo2 400
When a brown-out condition is detected, the signal "BO_NOK" turns off the circuit (refer to block diagram).
Start of PFC Operation VSIN
2 @ Vac @ sin(Rt)
EMI Filter
+ -
2 @ Vac 0
Figure 68. Brown-Out Block Thermal Shutdown (TSD)
Figure 69. Typical Input Voltage of a PFC Stage
An internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 150_C typically. The output stage is then enabled once the temperature drops below about 100_C (50_C hysteresis). The temperature shutdown keeps active as long as the circuit is not reset, that is, as long as VCC keeps higher than VCCRESET. The reset action forces the TSD threshold to be the upper one (150C). This ensures that any cold startup will be done with the right TSD level.
Output Drive Section
the voltage reference used for the regulation and the overvoltage protection. The circuit also incorporates a precise current reference (IREF) that allows the Overcurrent Limitation to feature a 6% accuracy over the temperature range.
OFF Mode
The output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. The gate drive is kept in a sinking mode whenever the Undervoltage Lockout is active or more generally whenever the circuit is off (i.e., when the "Fault Latch" of the block diagram is high or when the HV current source is on). Its high current capability (-500 mA/+800 mA) allows it to effectively drive high gate charge power MOSFET.
Reference Section
The circuit features an accurate internal reference voltage (VREF). VREF is optimized to be 3% accurate over the temperature range (the typical value is 2.5 V). VREF is
As previously mentioned, the circuit turns off in the following cases: * When the high voltage, startup current source charges the VCC capacitor. * When one of the following major faults is detected: * Incorrect feeding of the circuit ("UVLO" high when VCChttp://onsemi.com
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NCP1605
More specifically, when the circuit is in OFF state: * The drive output is kept low * All the blocks are off except: 1. The UVLO circuitry that keeps monitoring the VCC voltage and controlling the startup current source accordingly. 2. The TSD (thermal shutdown) 3. The "STDWN" latch that stores its output state. 4. The Undervoltage Protection ("UVP"). 5. The brown-out circuitry. One must note that the comparator is reset during the latched-off phase so that its threshold is the upper one (1 V) when the circuit enters the active phase (refer to next "VCC sequences" section). 6. The high voltage, startup current source when the circuit is in startup phase (that is when VCC is lower than VCCSTUP).
* The Pin 3 capacitor is discharged and kept grounded
along the OFF time, to initialize it for the next operating sequence, where it must be slowly and gradually charged to offer some soft-start. The "pfcOK" pin is grounded. The output of the "VTON processing block" is grounded
* *
VCC Sequences
The following table summarizes the state of the circuit in accordance to the VCC level.
"OFF" is Low VCC Conditions VCC exceeds VCCON the circuit enters the working phase VCC drops below VCCOFF the circuit enters the latched-off phase VCC goes below VCCSTUP the circuit enters the startup phase (no condition forces the circuit off) The startup current source is disabled The circuit is fully active The circuit is in OFF state The brown-out block resets during the latched-off phase so that its comparator threshold is forced to be the upper one (1 V) The high voltage, startup current source turns on to charge VCC. The drive output and the "pfcOK" are in low state (the circuit is off) All the circuit blocks are reset except: The thermal shutdown (TSD) and the brown-out block that keep operating The "STDWN" latch. The high voltage, startup current source is on. The whole circuitry is reset including the "TSD" and the "STDWN" latch. After reset, the TSD threshold is 150C and the output of the "STDWN latch" is low.
"OFF" is High (due to some protection like the thermal shutdown) The startup current source is disabled The circuit is in OFF state The circuit is in OFF state The brown-out block resets during the latched-off phase so that its comparator threshold is forced to be the upper one (1 V) The high voltage, startup current source turns on to charge VCC. The drive output and the "pfcOK" are in low state (the circuit is off) All the circuit blocks are reset except: The thermal shutdown (TSD) and the brown-out block that keep operating The "STDWN" latch. The high voltage, startup current source is on. The whole circuitry is reset including the "TSD" and the "STDWN" latch. After reset, the TSD threshold is 150C and the output of the "STDWN latch" is low.
VCC goes below VCCRESET the circuit resets
* In case of normal conditions (Figure 70). * As a function of the brown-out pin voltage (Figure 71).
The figures on the following pages portray the circuit behavior during a startup phase:
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NCP1605
Remarks:
The VCONTROL signal does not necessarily reach its clamp level (3.7 V) depending of the load and of the system time constants. In particular, if the circuit starts operation in light load and if the bulk capacitor is not too large, the output voltage VOUT generally exceeds the regulation level while VCONTROL keeps below its upper limit.
The output voltage exhibits a 100 or 120 Hz ripple (at twice the line frequency). This ripple is also present in the VCONTROL voltage even if it is attenuated due to the regulation low bandwidth. Like that of VOUT, this ripple is not represented in Figure 70, for the sake of the clarity.
VCCON VCC VCCOFF VCCSTUP 1V
VOUT
VOUT Regulation Level
VCONTROL MAX = 3.7 V
VCONTROL These re-activations of "Flag1" result from VOUT 100 or 120 Hz ripple (not represented here for the sake of clarity) Flag1
Circuit State
OFF
pfcOK
Drive Output
Figure 70. Startup Phase in Normal Conditions
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NCP1605
The Circuit is Off Low Consumption VCCON VCC 1V VCCOFF VCCSTUP
VOUT
Vout Regulation Level
1V 0.5 V Brown-Out Pin Voltage
Drive Output
Circuit State
OFF
pfcOK
Figure 71. Startup and Brown Out Conditions
When the high voltage, startup current source is on, the brown-out is active and its threshold is the upper one (VBO = VBOH = 1 V).
Fault Management Block
When any of the following faults is detected: brown-out ("BO_NOK"), Undervoltage ("UVP"), shutdown ("STDWN"), Die Overtemperature ("TSD"), the circuit immediately turns off and recovers operation as soon as the fault disappears. In case of UVLO (VCC too low to allow operation), the circuit keeps off until the end of the next VCC charge phase by the HV startup current source. The following block diagram details the function.
Internal Thermal Shutdown TSD UVP Stdwn BO_NOK
UVLO (VccS
Q UVLO Latch R OFF
HVCS_ON
Figure 72. Fault Management Block
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NCP1605
Bulk BOon
BOoff
Single Hiccup VCC VCCon Internal BOok VCCoff
Drive
Figure 73.
The above figure shows how the circuit recovers after a brown-out event.
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NCP1605
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE K
-A-
16 9
-B- P
1 8
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12 16
1
16X
0.58
1.27 PITCH 8 9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Soft-Skip is a trademark of Semiconductor Components Industries, LLC (SCILLC). The products described herein, may be covered by the following U.S. patents: 5,502,370 6,271,735, 6,362,067, 6,970,365. There may be other patents pending
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCP1605/D

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